Reverse design is traditionally referred to as a "bottom up" design method, also called reverse design. The reference to "reverse design" seems to make it easy to associate with infringement of other people's intellectual property rights. In fact, reverse design is the same as forward design. It is only a technical means of IC design, and it uses reverse design to obtain advanced design ideas of others. In their own chip design, it cannot be said that intellectual property rights are violated. Especially for beginner IC design personnel, by learning and researching more mature circuit layouts, related circuit design experience can be rapidly increased, and the entire IC design process can be quickly familiarized with and the IC design knowledge system can be improved.
At present, China's IC design industry is still in the stage of learning to imitate foreign countries. As early as a few years ago, China's IC design companies often copied foreign chips completely. In recent years, with the improvement of intellectual property awareness, people have been able to take the right approach to reverse design, which is to use reverse design to design their own chips. The reverse design flow is just the opposite of the forward design. From the flow point of view, the chip package must be removed first, then the chip should be peeled off, and the peeled-off chip should be photographed and analyzed. With the increase of the complexity of the chip, a simple camera can no longer effectively analyze the chip. The core vision company has launched Chiplogic software. Other reverse design companies have also launched their own reverse software, using software to achieve the analysis of the chip. Greatly improve the efficiency of the analysis.
Reverse design is ideal for analog chip designs, such as analog circuits such as ADCs, DACs, and phase-locked loops, because analog circuit designs often rely on experience. In addition, it is suitable for a digital circuit of 100,000 or less, and for a mixed-signal circuit, it is suitable for an analog part of the reverse design service. In terms of time, common reverse designs often take 3-5 months, while digital circuits with less than 100,000 gates usually take 2-3 months to reverse design.
The most important thing for reverse design is to seamlessly connect with the forward design. Therefore, in addition to most of the reverse extraction software, EDA vendor software must be used for layout and verification (such as Cadence) during the design process. At present, in China, in addition to the core vision company, Shanghai's San Jing Company and Taiwan Yishuo also provide reverse design services; internationally renowned reverse design companies mainly include Chipworks and Semiconductors Insights (SI). Reverse design companies can provide complete anatomy and circuit extraction services, the most insufficient is the in-depth analysis of the circuit, which requires the designer to complete the relevant work.
Reverse design flowâ—† Corrosion
- Corrosion of the plastic enclosure, visible first layer of metal
Ninety-five percent sulfuric acid is generally used for cooking. Concentrated nitric acid may be used depending on the molding material.
- Corrosion of metal aluminum layer, can see polycrystalline and active area
Using hot phosphoric acid
- When there are multiple layers of metal, it is necessary to use hydrofluoric acid to remove silicon after removing a layer of metal
- De-polysilicon, stained to reveal P-well and N-well
- Other details of processing, longitudinal structure anatomy (SEM scanning electron microscopy / TEM transmission electron microscopy or doping concentration curve test, generally require IC anatomy do not, are standard processes, discrete devices generally need to do)
â—† Photo jigsaw
- Each layer is etched and sub-area photographed
- Each layer of metal mosaic, each layer poly mosaic, active area mosaic
- Process splice diagrams into software-recognizable image files using software components provided by chiplogic software or other reverse companies
- The pictures are processed in proportion. The software can directly test MOS aspect ratio and minimum line width, etc.
- The processed image group can see multiple layers of images in the software at the same time. This is difficult to do manually.
- General microscopes with CCDs cannot be used for chip photographic puzzles and require specialized microscope equipment
â—† Labeling blocks
- Mark each pin function
- Starting from the chip pins, roughly distinguish the functional areas of the chip from the full layout
- Generally, the power and ground lines are marked first to improve the efficiency of the later analysis
â—† Extract and organize circuit
- Digital circuits need to merge similar graphics, such as NAND gates, NOR gates, flip-flops, etc.
- The proposed circuit is drawn by circuit drawing software (ViewWork, Laker, Cadence, etc.), and the circuit layout is easy to understand so that other people can see the function of the circuit you extracted.
- The speed of the extraction circuit is determined entirely by the experience level of the charter
-Chiplogic software is to connect the components according to the position of the layout. If you do not sort the circuit, you cannot see the connection and function of each module. Therefore, it is impossible to complete the division and analysis of circuit function blocks by software.
â—† Analysis circuit
- Extract the circuit into a circuit diagram, and enter the geometric parameters (MOS is wide-length ratio)
- Through your analysis, the circuit function is clear and the circuit connection is correct
â—† Simulation verification, circuit adjustment
- Functional verification of the circuit
- Analog circuits typically use Hspice, Cadence, etc. Small-scale digital circuits use tools such as Cadence, Hsim, etc.
- Adjust circuit according to new process
- Verification after adjustment
â—† layout drawing verification and post simulation
- Drawing layouts based on new process documents
- Layout DRC, LVS, Parasitic Parameter Extraction (Dracula, Assura, Calibre, etc.)
- Extracted netlists for simulation verification and comparison with previous simulation results
- Layout export GDS file, Tape out
â—† IC back-end design flow chart
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